.file	"vu.c"
	.intel_syntax noprefix
	.text
	.section .rdata,"dr"
.LC0:
	.ascii "C2\12RESERVED\0"
	.text
	.p2align 4,,15
	.globl	res_V
	.def	res_V;	.scl	2;	.type	32;	.endef
	.seh_proc	res_V
res_V:
	sub	rsp, 40
	.seh_stackalloc	40
	.seh_endprologue
	lea	rcx, .LC0[rip]
	call	message
	pxor	xmm0, xmm0
	add	rsp, 40
	ret
	.seh_endproc
	.section .rdata,"dr"
.LC1:
	.ascii "VMUL IQ\0"
	.text
	.p2align 4,,15
	.globl	res_M
	.def	res_M;	.scl	2;	.type	32;	.endef
	.seh_proc	res_M
res_M:
	sub	rsp, 40
	.seh_stackalloc	40
	.seh_endprologue
	lea	rcx, .LC1[rip]
	call	message
	lea	rcx, .LC0[rip]
	call	message
	pxor	xmm0, xmm0
	add	rsp, 40
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	get_VCO
	.def	get_VCO;	.scl	2;	.type	32;	.endef
	.seh_proc	get_VCO
get_VCO:
	.seh_endprologue
	movdqa	xmm1, XMMWORD PTR cf_ne[rip]
	movdqa	xmm0, XMMWORD PTR cf_co[rip]
	psllw	xmm1, 15
	psllw	xmm0, 15
	packsswb	xmm0, xmm1
	pmovmskb	eax, xmm0
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	get_VCC
	.def	get_VCC;	.scl	2;	.type	32;	.endef
	.seh_proc	get_VCC
get_VCC:
	.seh_endprologue
	movdqa	xmm1, XMMWORD PTR cf_clip[rip]
	movdqa	xmm0, XMMWORD PTR cf_comp[rip]
	psllw	xmm1, 15
	psllw	xmm0, 15
	packsswb	xmm0, xmm1
	pmovmskb	eax, xmm0
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	get_VCE
	.def	get_VCE;	.scl	2;	.type	32;	.endef
	.seh_proc	get_VCE
get_VCE:
	.seh_endprologue
	movdqa	xmm0, XMMWORD PTR cf_vce[rip]
	pxor	xmm1, xmm1
	psllw	xmm0, 15
	packsswb	xmm0, xmm1
	pmovmskb	eax, xmm0
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	set_VCO
	.def	set_VCO;	.scl	2;	.type	32;	.endef
	.seh_proc	set_VCO
set_VCO:
	.seh_endprologue
	movzx	eax, cx
	and	ecx, 1
	mov	edx, eax
	mov	WORD PTR cf_co[rip], cx
	sar	edx
	and	edx, 1
	mov	WORD PTR 2+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 2
	and	edx, 1
	mov	WORD PTR 4+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 3
	and	edx, 1
	mov	WORD PTR 6+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 4
	and	edx, 1
	mov	WORD PTR 8+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 5
	and	edx, 1
	mov	WORD PTR 10+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 6
	and	edx, 1
	mov	WORD PTR 12+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 7
	and	edx, 1
	mov	WORD PTR 14+cf_co[rip], dx
	mov	edx, eax
	sar	edx, 8
	and	edx, 1
	mov	WORD PTR cf_ne[rip], dx
	mov	edx, eax
	sar	edx, 9
	and	edx, 1
	mov	WORD PTR 2+cf_ne[rip], dx
	mov	edx, eax
	sar	edx, 10
	and	edx, 1
	mov	WORD PTR 4+cf_ne[rip], dx
	mov	edx, eax
	sar	edx, 11
	and	edx, 1
	mov	WORD PTR 6+cf_ne[rip], dx
	mov	edx, eax
	sar	edx, 12
	and	edx, 1
	mov	WORD PTR 8+cf_ne[rip], dx
	mov	edx, eax
	sar	edx, 13
	and	edx, 1
	mov	WORD PTR 10+cf_ne[rip], dx
	mov	edx, eax
	sar	eax, 15
	sar	edx, 14
	mov	WORD PTR 14+cf_ne[rip], ax
	and	edx, 1
	mov	WORD PTR 12+cf_ne[rip], dx
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	set_VCC
	.def	set_VCC;	.scl	2;	.type	32;	.endef
	.seh_proc	set_VCC
set_VCC:
	.seh_endprologue
	movzx	eax, cx
	and	ecx, 1
	mov	edx, eax
	mov	WORD PTR cf_comp[rip], cx
	sar	edx
	and	edx, 1
	mov	WORD PTR 2+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 2
	and	edx, 1
	mov	WORD PTR 4+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 3
	and	edx, 1
	mov	WORD PTR 6+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 4
	and	edx, 1
	mov	WORD PTR 8+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 5
	and	edx, 1
	mov	WORD PTR 10+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 6
	and	edx, 1
	mov	WORD PTR 12+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 7
	and	edx, 1
	mov	WORD PTR 14+cf_comp[rip], dx
	mov	edx, eax
	sar	edx, 8
	and	edx, 1
	mov	WORD PTR cf_clip[rip], dx
	mov	edx, eax
	sar	edx, 9
	and	edx, 1
	mov	WORD PTR 2+cf_clip[rip], dx
	mov	edx, eax
	sar	edx, 10
	and	edx, 1
	mov	WORD PTR 4+cf_clip[rip], dx
	mov	edx, eax
	sar	edx, 11
	and	edx, 1
	mov	WORD PTR 6+cf_clip[rip], dx
	mov	edx, eax
	sar	edx, 12
	and	edx, 1
	mov	WORD PTR 8+cf_clip[rip], dx
	mov	edx, eax
	sar	edx, 13
	and	edx, 1
	mov	WORD PTR 10+cf_clip[rip], dx
	mov	edx, eax
	sar	eax, 15
	sar	edx, 14
	mov	WORD PTR 14+cf_clip[rip], ax
	and	edx, 1
	mov	WORD PTR 12+cf_clip[rip], dx
	ret
	.seh_endproc
	.p2align 4,,15
	.globl	set_VCE
	.def	set_VCE;	.scl	2;	.type	32;	.endef
	.seh_proc	set_VCE
set_VCE:
	.seh_endprologue
	movzx	eax, cl
	and	ecx, 1
	mov	edx, eax
	mov	WORD PTR cf_vce[rip], cx
	sar	edx
	and	edx, 1
	mov	WORD PTR 2+cf_vce[rip], dx
	mov	edx, eax
	sar	edx, 2
	and	edx, 1
	mov	WORD PTR 4+cf_vce[rip], dx
	mov	edx, eax
	sar	edx, 3
	and	edx, 1
	mov	WORD PTR 6+cf_vce[rip], dx
	mov	edx, eax
	sar	edx, 4
	and	edx, 1
	mov	WORD PTR 8+cf_vce[rip], dx
	mov	edx, eax
	sar	edx, 5
	and	edx, 1
	mov	WORD PTR 10+cf_vce[rip], dx
	mov	edx, eax
	sar	eax, 7
	sar	edx, 6
	mov	WORD PTR 14+cf_vce[rip], ax
	and	edx, 1
	mov	WORD PTR 12+cf_vce[rip], dx
	ret
	.seh_endproc
	.globl	COP2_C2
	.data
	.align 32
COP2_C2:
	.quad	VMULF
	.quad	VMULU
	.quad	res_M
	.quad	res_M
	.quad	VMUDL
	.quad	VMUDM
	.quad	VMUDN
	.quad	VMUDH
	.quad	VMACF
	.quad	VMACU
	.quad	res_M
	.quad	res_M
	.quad	VMADL
	.quad	VMADM
	.quad	VMADN
	.quad	VMADH
	.quad	VADD
	.quad	VSUB
	.quad	res_V
	.quad	VABS
	.quad	VADDC
	.quad	VSUBC
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	VSAW
	.quad	res_V
	.quad	res_V
	.quad	VLT
	.quad	VEQ
	.quad	VNE
	.quad	VGE
	.quad	VCL
	.quad	VCH
	.quad	VCR
	.quad	VMRG
	.quad	VAND
	.quad	VNAND
	.quad	VOR
	.quad	VNOR
	.quad	VXOR
	.quad	VNXOR
	.quad	res_V
	.quad	res_V
	.quad	VRCP
	.quad	VRCPL
	.quad	VRCPH
	.quad	VMOV
	.quad	VRSQ
	.quad	VRSQL
	.quad	VRSQH
	.quad	VNOP
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.quad	res_V
	.comm	cf_vce, 16, 4
	.comm	cf_comp, 16, 4
	.comm	cf_clip, 16, 4
	.comm	cf_co, 16, 4
	.comm	cf_ne, 16, 4
	.comm	VACC, 48, 4
	.comm	VR, 1024, 4
	.ident	"GCC: (Rev1, Built by MSYS2 project) 7.3.0"
	.def	message;	.scl	2;	.type	32;	.endef
	.def	VMULF;	.scl	2;	.type	32;	.endef
	.def	VMULU;	.scl	2;	.type	32;	.endef
	.def	VMUDL;	.scl	2;	.type	32;	.endef
	.def	VMUDM;	.scl	2;	.type	32;	.endef
	.def	VMUDN;	.scl	2;	.type	32;	.endef
	.def	VMUDH;	.scl	2;	.type	32;	.endef
	.def	VMACF;	.scl	2;	.type	32;	.endef
	.def	VMACU;	.scl	2;	.type	32;	.endef
	.def	VMADL;	.scl	2;	.type	32;	.endef
	.def	VMADM;	.scl	2;	.type	32;	.endef
	.def	VMADN;	.scl	2;	.type	32;	.endef
	.def	VMADH;	.scl	2;	.type	32;	.endef
	.def	VADD;	.scl	2;	.type	32;	.endef
	.def	VSUB;	.scl	2;	.type	32;	.endef
	.def	VABS;	.scl	2;	.type	32;	.endef
	.def	VADDC;	.scl	2;	.type	32;	.endef
	.def	VSUBC;	.scl	2;	.type	32;	.endef
	.def	VSAW;	.scl	2;	.type	32;	.endef
	.def	VLT;	.scl	2;	.type	32;	.endef
	.def	VEQ;	.scl	2;	.type	32;	.endef
	.def	VNE;	.scl	2;	.type	32;	.endef
	.def	VGE;	.scl	2;	.type	32;	.endef
	.def	VCL;	.scl	2;	.type	32;	.endef
	.def	VCH;	.scl	2;	.type	32;	.endef
	.def	VCR;	.scl	2;	.type	32;	.endef
	.def	VMRG;	.scl	2;	.type	32;	.endef
	.def	VAND;	.scl	2;	.type	32;	.endef
	.def	VNAND;	.scl	2;	.type	32;	.endef
	.def	VOR;	.scl	2;	.type	32;	.endef
	.def	VNOR;	.scl	2;	.type	32;	.endef
	.def	VXOR;	.scl	2;	.type	32;	.endef
	.def	VNXOR;	.scl	2;	.type	32;	.endef
	.def	VRCP;	.scl	2;	.type	32;	.endef
	.def	VRCPL;	.scl	2;	.type	32;	.endef
	.def	VRCPH;	.scl	2;	.type	32;	.endef
	.def	VMOV;	.scl	2;	.type	32;	.endef
	.def	VRSQ;	.scl	2;	.type	32;	.endef
	.def	VRSQL;	.scl	2;	.type	32;	.endef
	.def	VRSQH;	.scl	2;	.type	32;	.endef
	.def	VNOP;	.scl	2;	.type	32;	.endef